The IC manufacturing process, which includes IC fabrication and packaging, is not a perfect one, and defects are often introduced which prevent a manufactured IC device from working as intended. Customers have high expectations for the quality and reliability of semiconductor products, and typically only a few hundred defective parts per million (DPPM) are allowed with a lifespan of several years. Aside from defects introduced during the design phase, IC manufacturing test is primarily responsible for achieving this daunting reliability objective.
Several types of testing are performed at different stages of the IC manufacturing process. For one testing type, automatic test-pattern generation (ATPG) techniques are utilized to achieve sufficient defect coverage during the wafer and final test stages of the IC manufacturing process. As IC technology advances, test patterns, in addition to the traditional stuck-at vectors, that target delay faults and various other kinds of subtle errors (e.g., latent or hidden defects), including, but not limited to, signal integrity faults, also become essential to guarantee test quality. The associated large number of test patterns not only requires considerable testing time on automatic test equipment (ATE), which is costly, but also indirectly results in more false rejections and thus lowers the manufacturing yield of the integrated circuits.
On the other hand, accelerated testing methods, such as, for example, burn-in testing, are often used to screen and discard those ICs with early-life failures (e.g., infant mortality failures) to thereby enhance product reliability. For modern ICs fabricated with the latest technology, however, it is becoming increasingly challenging to formulate and control appropriate stress conditions for the ICs during the burn-in process, which undesirably makes such accelerated testing methods a bottleneck in the manufacturing test process.